1. Field of the Invention
The present invention is related to a cache memory control technology in an external storage subsystem having a cache memory, and more particularly to a cache memory control technology in an external storage subsystem which is shared by plural host units or an information storage system which includes host units.
2. Description of the Prior Art
Information processing systems with increasing performance and scale require external storage subsystems with improved performance. Array type external storage subsystems having large capacity cache memory are now a leading choice of consumers. To increase the performance of such systems, it is important to provide a more efficient control method for the large capacity cache memory. Various methods for control of the large capacity cache memory are described below.
One method uses the frequency of access of data management information in a file system so that frequently used data management information resides on a cache memory, and less frequently used data management information is excluded from the cache memory. Such a system is disclosed in Japanese patent unexamined publication 06-124239.
Another method controls the system by using a caching method based on common algorithms, for example, the least recently used algorithm (LRU). In such systems, the miss-hit rate is examined for each program. If the miss-hit rate is higher than an appointed value, caching is not used in execution of the program after that. Consequently, the caching frequency is reduced correspondingly, and the area of the cache memory consumed by the program is used for another program. This second program presumably has a higher hit rate than the appointed value. Such a system is disclosed in Japanese patent unexamined publication 05-189307.
A method in which an instruction, which enables a program to explicitly designate which data on a main memory is to be placed in a cache memory and provides a control circuit which copies or transfers data from the main memory to the cache memory according to the designation is also known. In this system a circuit which stores the transferred data on the cache memory, and a circuit which cancels storage of the resident data, are provided. A particular program, to be given priority, controls the caching corresponding to characteristics of its processing procedure. As an example of such, see Japanese patent unexamined publication 07-287669.